In source synchronous systems, a sending circuit may send both data signals carrying data and a clock signal to a receiving circuit. The receiving circuit may use the clock signal to identify the data values of the data carried by the data signals. In particular, the receiving circuit may determine when to identify levels of data pulses identifying the data values in response to detecting transitions of the clock signal. Ideally, the clock transitions occur at optimal times that optimize the receiving circuit's ability to identify the correct levels of the data pulses. A deviation of the clock transitions from their optimal times may be referred to as skew between the clock signal and the data signal. Too large of skew between the data and clock signals may cause the receiving circuit to incorrectly identify the levels of the data pulses. Increases in frequency of the data and clock signals serve to magnify the problems that skew can have. Thus, as frequencies increase, processes that can correct for skew are increasingly important. At the same time, it is often desirable to communicate data from the sending circuit to the receiving circuit as quick as possible. Thus, efficient skew correction processes that require relatively small overhead may be desirable.